1. Field of the Invention
This invention relates to electrical divide-by circuits for dividing down signals, and more particularly to dynamic d-type flip-flop circuits used in digital devices such as microprocessors, digital signal processors, prescalers and digital counters.
2. Description of Related Art
Digital devices frequently utilize circuits that are capable of storing data (i.e., xe2x80x9cmemoryxe2x80x9d circuits). One exemplary basic memory circuit is the well-known d-type flip-flop (DFF). Exemplary digital devices that utilize DFFs include microprocessors, digital signal processors, prescalers, and digital counters.
One objective of DFF design is to increase the maximum operating frequency of the DFF circuits. The xe2x80x9cmaximum operating frequencyxe2x80x9d (MOF) is defined as the highest clock frequency at which a DFF maintains stable operation (ie., maintains accurate data storage). Several exemplary xe2x80x9cdynamicxe2x80x9d DFF circuits are now described. The term dynamic refers to the well-known, low-power, high-speed technique of temporarily storing digital information (e.g., a data bit) in the nodal capacitance at the gate of a MOS transistor. This capacitance can include both the parasitic and gate capacitance.
A first exemplary DFF circuit is referred to as a true single phase clock d-type flip-flip (TSPC DFF) circuit and is described in more detail in an article by Yuan and Svensson, entitled xe2x80x9cHigh-Speed CMOS Circuit Techniquexe2x80x9d published in the IEEE Journal of Solid State Circuits, 24(1), pages 62-70 in 1989 by IEEE, which is hereby incorporated by reference herein for its teachings on digital circuits design. The TSPC DFF is widely implemented as a high-speed DFF in speed-critical applications.
FIG. 1 is a schematic diagram of an exemplary TSPC DFF circuit. As shown in FIG. 1, the exemplary TSPC DFF circuit 100 includes nine transistors: N114, N216, N326, N436, P112, P222, P324, P432 and P534. For simplification, the description of the inventive uses the following nomenclature: transistors with an xe2x80x9cNxe2x80x9d prefix (e.g., N326) comprise NMOS transistors. Transistors with a xe2x80x9cPxe2x80x9d prefix (e.g., P534) comprise PMOS transistors. Those skilled in the electrical circuit design arts shall recognize that alternative terms can be used without departing from the scope or spirit of the present invention. A clock signal inputs to 4 transistors: N114, P222, N326 and P534.
The exemplary TSPC DFF circuit 100 typically comprises three stages. Each stage typically comprises a set of xe2x80x9cstackedxe2x80x9d transistors, wherein elements are vertically xe2x80x9cstackedxe2x80x9d. For example, a first stage comprises transistors P112, N114 and N216; a second stage comprises transistors P222, P324 and N326; and a third stage comprises transistors P432, P534 and N436. In the exemplary TSPC DFF circuit 100 the relative sizes of transistors within each stage are not critical to the proper operation of the circuit. The exemplary TSPC DFF circuit 100 is described in greater detail in the above-incorporated article by Yuan and Svensson, and thus is not described in more detail herein. A stand exemplary DFF circuit is now described with reference to FIG. 2.
A second exemplary DFF circuit improves upon the first exemplary DFF circuit by implementing well-known xe2x80x9cratioed logicxe2x80x9d techniques. To function properly, ratioed logic techniques require that the PMOS and NMOS transistors within a stage have a specific transistor size (ie., dimension or width/length (W/L)) ratio. Ratioed logic techniques are well known, and thus are not described in more detail herein. Exemplary ratioed logic techniques are described in a book by Van Valkenburg, entitled xe2x80x9cReference Data for Engineers, eighth editionxe2x80x9d published in 1995 by Sams publishing, chapter 20, pages 20-35 and 20-36, which is hereby incorporated by reference herein for its teachings on ratioed logic circuit design techniques. Using ratioed logic techniques advantageously reduces the number of transistors needed in circuit implementations, and thus, increases circuit speed.
The second exemplary DFF circuit comprises only 7 transistors, whereas the first exemplary TSPC DFF circuit 100 comprises 9 transistors. The second exemplary circuit is referred to as a xe2x80x9cNew Dynamic D-Type Flip-Flopxe2x80x9d (ND DFF) and is described in detail in an article by Chang et al., entitled xe2x80x9cA 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,xe2x80x9d published in the IEEE Journal of Solid State Circuits, 31(5), at pages 749-752 in 1996 by IEEE. The article is hereby incorporated by reference herein for its teachings on digital circuit design. FIG. 2 is a schematic diagram of an exemplary ND DFF. As shown in FIG. 2, the exemplary ND DFF circuit 200 comprises 7 transistors: N114, N216, N326, N436, P112, P222 and P534. A clock signal is input into 3 transistors: N114, N326 and P534. The exemplary ND DFF 200 advantageously exhibits less clock loading than does the TSPC DFF described above with reference to FIG. 1. Specifically, the clock driver of the TSPC DFF 100 of FIG. 1 drives four transistors (specifically, the transistors N114, P222, N326 and P534), whereas the clock driver of the exemplary ND DFF 200 of FIG. 2 drives only three transistors (N114, N326 and P534).
The ND DFF circuit 200 typically includes three transistor stages. A first stage comprises the transistors P112, N114 and N216; a second stage comprises the transistors P222 and N326; and a third stage comprises the transistors P534 and N436. The second stage of the exemplary ND DFF circuit 200 uses a ratioed logic technique. The ratioed logic technique requires a transistor size ratio between P2 and N3 to be selected so that when P2 and N3 are both xe2x80x9conxe2x80x9d, (i.e., conducting) node B is below the VIL of N4. Similarly, the third stage also implements ratioed logic where the QB6 is below the VIL of an output buffer (not shown in FIG. 2) connected to the QB6. The exemplary ND DFF 200 is described in greater detail in the above-incorporated article by Chang et al., and thus is not described in more detail herein. A third exemplary DFF circuit is now described with reference to FIG. 3.
A third exemplary DFF circuit improves upon the second exemplary DFF circuit by using fewer transistors, and thereby improves circuit performance. The third exemplary DFF circuit includes only 6 transistors, whereas the second exemplary DFF circuit 200 includes 7 transistors. The third exemplary circuit is referred to as an xe2x80x9cExtended True-Single-Phase-Clock D-Type Flip-Flopxe2x80x9d (E-TSPC DFF).
FIG. 3 is a schematic diagram of an exemplary E-TSPC DFF. As shown in FIG. 3, the exemplary E-TSPC DFF circuit 300 includes 6 transistors: N114, N326, N436, P112, P222 and P534. A clock signal (referred to hereinafter as either xe2x80x9cCLKxe2x80x9d or xe2x80x9cCxe2x80x9d) 4, 4xe2x80x2, and 4xe2x80x3 inputs respectively to 3 transistors: N114, N326 and P534. The exemplary E-TSPC circuit 300 includes three transistor stages. As shown in FIG. 3, a first stage 51 includes the stacked transistors P112 and N114; a second stage 52 includes the stacked transistors P222 and N326; and a third stage 53 includes the stacked transistors P534 and N436. The third exemplary DFF circuit 300 is substantially similar to the second exemplary DFF circuit 200 (FIG. 2), and thus is not described in more detail herein. Identical components function similarly in both circuits.
One embodiment of the third exemplary DFF circuit 300 is referred to as a xe2x80x9cRatioed Logic Extended True-Single-Phase-Clock D-type Flip-Flopxe2x80x9d (RL E-TSPC DFF) and is described in an article by Soares and Van Noije, entitled xe2x80x9cA 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC),xe2x80x9d published in 1999 in the IEEE Journal of Solid State Circuits, 34(1), at pages 97-102 (and at FIG. 6), by IEEE. The article is hereby incorporated by reference herein for its teachings on digital circuit design. The RL E-TSPC implements ratioed logic techniques for all transistor stages (i.e., the first stage 51, the second stage 52 and the third stage 53).
Although the RL E-TSPC DFF is substantially similar in design to the second exemplary DFF circuit 200 (FIG. 2), all three transistor stages of the RL E-TSPC DFF use ratioed logic design. Specifically, the first stage 51 utilizes a ratioed logic technique which is implemented using only the transistors P112 and N114. The ratioed logic technique of the first stage requires that the transistor size ratio between the transistor P112 and the transistor N114 be selected so that the state of Node A42 remains at a logical high level (referred to hereinafter simply as xe2x80x9chighxe2x80x9d) regardless of the state of the input CLK4, 4xe2x80x2, 4xe2x80x3, when the state at the input D2 is at a logical low level (referred to hereinafter as xe2x80x9clowxe2x80x9d). Stated in other terms, the ratioed logic technique of the first stage ensures that Node A remain high when P1 is conducting, and low when P1 is not conducting. One exemplary transistor size ratio is four-to-one (P1-to-N1) or greater.
Disadvantageously, the ratioed logic technique of the first stage causes a decrease in the maximum operating speed and frequency of the RL E-TSPC DFF embodiment of the E-TSPC DFF 300. This decrease in operating speed results from the requirement that the transistor size ratio of P112 to N114 ensures that, when D is low, the node A 42 remains high regardless of the value of the input CLK. Therefore, transistor P112 must be much larger than the transistor N114 (e.g., P112 must be at least four times larger than N114). This requirement creates extremely mismatched transistor sizes because the drive strength of PMOS transistors is typically weaker than the drive strength of similarly sized NMOS transistors. Thus, the maximum operating speed and frequency of the RL E-TSPC DFF is decreased.
Another disadvantage associated with the TSPC DFF circuit 100, ND DFF circuit 200 and the RL E-TSPC circuit 300 (FIGS. 1-3, respectively) is that the operating speeds are relatively sensitive to parasitic capacitances. Specifically, and referring now to FIGS. 1-3, nodes A42 and B44 are very sensitive to parasitic capacitances when the TSPC DFF 100, ND DFF 200 and RL E-TSPC 300 circuits are manufactured using bulk silicon material. This sensitivity to parasite capacitances detrimentally affects circuit performance.
Therefore, a need exists for a dynamic d-type flip-flop circuit that operates at high speeds and has increased maximum operating frequencies. The dynamic DFF should be relatively simple to implement. Such a dynamic DFF circuit should be manufactured using transistors having sizes that allow the circuit to operate reliably near maximum speeds. The present invention provides such a dynamic d-type flip-flop circuit.
The present invention is a novel dynamic DFF method and apparatus for use in complex circuits. The dynamic DFF method and apparatus utilizes an inventive transistor design, and thus obviates the need for ratioed logic transistors in a first stage of the circuit. An exemplary CMOS substrate that can be utilized with the present invention is fabricated using Silicon-on-Insulator (SOI) technologies, which include, for example, separation by implanted oxygen (SIMOX), silicon-on-sapphire, bulk silicon and UTSi.
The method and apparatus of the present invention improves the operating speed of dynamic d-type flip-flop circuits. Specifically, the present invention does not require use of a ratioed logic design in a first stage of transistors, and thus PMOS and NMOS transistors in the first stage are not required to have disproportionate P-to-N transistor size ratios. Consequently, these transistors can have a transistor size ratio that provides increased operating speeds. The inventive circuit also consumes less power than the prior art designs. A number of embodiments of the present invention are described. In one embodiment, a dynamic DFF is described. Another embodiment of the present invention provides a dynamic DFF including a merged logic xe2x80x9cANDxe2x80x9d gate. The merged logic gate design includes the merged logic xe2x80x9cANDxe2x80x9d function at a negligible degradation is speed.
Several exemplary applications of the present invention are described. In a first exemplary application, the present inventive DFF is utilized in a divide-by-4/5 prescaler circuit. In a second exemplary application, the present inventive DFF is utilized in a divide-by-4/5 prescaler circuit having merged xe2x80x9cANDxe2x80x9d gates. In a third exemplary application, the present inventive DFF is utilized in a phase lock loop circuit.
The details of the several embodiments of the present invention are set forth in the accompanying drawings and the description provided below. Once the details of the invention are known, numerous additional innovations and changes will become obvious to those skilled in the art.